HP rp5400 Informações Técnicas descarregar pdf (Página 10)

Figure 2.2 is a block diagram of the rp5450 architecture. The rp5450 uses the “Astro” CEC, which

was specifically designed to provide no-compromise features and performance at a low-end price

point. Integrated within the single “Astro” chip is the memory and I/O controllers, with several

peripheral application-specific integrated circuits (ASICs) to control and drive the specific I/O and

memory buses.

The integrated rp5450 CEC design contributes to a significant reduction in memory latency over that

found in competitive systems. The memory controller supports two sets of integrated 8-slot memory

arrays, providing a total of sixteen DIMM slots.

The rp5450 uses a single 82.5MHz runway bus to provide 1.3GB/s of bandwidth to four PA-8600

or PA-8500 processors. The I/O controller in the rp5450 provides eight 250MB/s data channels.

This means an aggregate bandwidth of 2.1GB/s is available to the PCI slots and multi-function core

I/O.

The rp5400 architecture is similar to the rp5450. However, only half of the memory, processor, and

I/O capacity is utilized.

Figure 2.2 rp5450 architecture

System Bus

System Speeds and Feeds

System bus bandwidth 1.3GB/s

Memory bus bandwidth 1.3GB/s

I/O bandwidth total 2.1GB/s

Shared

PCI slots

Very Low

Latency

Memory

Controller

PA-8600

CPU

Memory

slots

Standard

Multifunction

Core I/O

DB-25 port

System Management

Ports

Ultra2 SCSI port

10/100Base-TX port

10/100Base-TX LAN console port

Optional internal

hot-plug Ultra2

SCSI disks

SCSI2

Optional DVD or

DAT internal

removable media

RS-232

Local Console

Remote Console

Gen Purpose

Hot-Plug PCI

Turbo slots

PA-8600

CPU

PA-8600

CPU

PA-8600

CPU

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 27 28

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