HP rp5400 Informações Técnicas Página 11

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low-latency
memory access
All four systems in the rp5400 series have sixteen memory slots. The rp5400 and rp5450 have all
sixteen slots laid out on the main system board. The rp5430 and rp5470, on the other hand, use
two 8-slot memory carrier boards. The memory for both systems is connected to the CEC through a
low-latency/high-bandwidth bus. With approximately half the latency of HP’s previous generation K-
Class server, the rp5400 series can supply the CPUs with requested data in a fraction of the time of
competitive systems.
The rp5400 series uses state-of-the-art SyncDRAM technology available in 256MB, 512MB, 1GB,
and 2GB DIMM pairs, all with advanced Error Checking and Correcting (ECC) protection to detect
and correct single-bit errors. The rp5470 and rp5450 support up to 16GB of total system memory.
The rp5400 and rp5430 support up to 8GB of memory. All sixteen memory slots are active in the
rp5400 and rp5430. These two systems will not boot, however, if more than 8GB of memory is
loaded. So plan your memory configurations appropriately.
The “Stretch” core electronics complex used in the rp5430 and rp5470 supports memory chip
spare. This high availability technology detects and corrects DRAM failures on memory DIMMs.
With chip spare, any single DRAM chip can fail and the system will continue to operate normally.
Chip spare is not supported on the 256MB DIMM pair, nor is it supported on the rp5400 of
rp5450.
To decrease memory latency and improve performance, the memory address lines are buffered three
times: once on the system board to drive each memory carrier, once on the memory carrier to drive
banks of DIMMs, and again on each DIMM before driving the memory components.
speeds and feeds
Tables 2.1, 2.2, and 2.3 show the theoretical maximum bandwidth for various system buses. This is
defined as the bus width multiplied by the frequency and number of buses.
Table 2.1 Maximum bandwidth for rp5470 system buses
# of buses (or controllers) maximum bus bandwidth aggregate bus bandwidth
twin-turbo PCI slots
2 500MB/s 1GB/s
turbo PCI slots
6 250MB/s 1.5GB/s
shared PCI slots
1 250MB/s 250MB/s
core I/O
1 250MB/s 250MB/s
I/O subsystem
1 (controller) 3.2GB/s 3.2GB/s
memory subsystem
2 2.15GB/s 4.3GB/s
CPU buses
2 2.15GB/s 4.3GB/s
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