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Land Listing and Signal Descriptions

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 45

4 Land Listing and Signal

Descriptions

This chapter provides the processor land assignment and signal descriptions.

4.1 Processor Land Assignments

This section contains the land listings for the processor. The land-out footprint is shown

in Figure 4-1 and Figure 4-2. These figures represent the land-out arranged by land

number and they show the physical location of each signal on the package land array

(top view). Table 4-1 provides a listing of all processor lands ordered alphabetically by

land (signal) name. Table 4-2 provides a listing of all processor lands ordered by land

number.

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 101 102

Dual-Core Intel 1
Processor 1
Contents 3
1, 2, 3, 4 6
Revision History 7
3000 Series Features 8
1 Introduction 9
1.1.1 Processor Terminology 10
1.2 References 11
1, 2, 5 12
2 Electrical Specifications 13
2.3 Voltage Identification 14
Electrical Specifications 17
Table 2-5. V 19
Figure 2-1. V 20
Table 2-6. V 20
(Sheet 1 of 2) 20
(Sheet 2 of 2) 21
Figure 2-2. V 21
Overshoot 22
2.6.4 Die Voltage Validation 22
2.7 Signaling Specifications 23
2.7.4 Clock Specifications 27
2.8 PECI DC Specifications 31
Table 2-3 for V 32
3 Package Mechanical 33
3.2 Processor Markings 39
INTEL® XEON® 40
SLxxx [COO] 40
2.33GHZ/4M/1333/06 40
Preliminary 41
Socket 775 41
Quadrants 41
Top View 41
4 Land Listing and Signal 43
Descriptions 43
Table 4-1. Alphabetical Land 46
Assignments (Sheet 1 of 20) 46
Assignments (Sheet 2 of 20) 46
Assignments (Sheet 3 of 20) 47
Assignments (Sheet 4 of 20) 47
Assignments (Sheet 5 of 20) 48
Assignments (Sheet 6 of 20) 48
Assignments (Sheet 7 of 20) 49
Assignments (Sheet 8 of 20) 49
Assignments (Sheet 9 of 20) 50
Assignments (Sheet 10 of 20) 50
Assignments (Sheet 11 of 20) 51
Assignments (Sheet 12 of 20) 51
Assignments (Sheet 13 of 20) 52
Assignments (Sheet 14 of 20) 52
Assignments (Sheet 15 of 20) 53
Assignments (Sheet 16 of 20) 53
Assignments (Sheet 17 of 20) 54
Assignments (Sheet 18 of 20) 54
Assignments (Sheet 19 of 20) 55
Assignments (Sheet 20 of 20) 55
(Sheet 1 of 20) 56
(Sheet 2 of 20) 56
(Sheet 3 of 20) 57
(Sheet 4 of 20) 57
(Sheet 5 of 20) 58
(Sheet 6 of 20) 58
(Sheet 7 of 20) 59
(Sheet 8 of 20) 59
(Sheet 9 of 20) 60
(Sheet 10 of 20) 60
(Sheet 11 of 20) 61
(Sheet 12 of 20) 61
(Sheet 13 of 20) 62
(Sheet 14 of 20) 62
(Sheet 15 of 20) 63
(Sheet 16 of 20) 63
(Sheet 17 of 20) 64
(Sheet 18 of 20) 64
(Sheet 19 of 20) 65
(Sheet 20 of 20) 65
5 Thermal Specifications and 73
Design Considerations 73
5.1.2 Thermal Metrology 78
5.2.1 Thermal Monitor 78
5.2.2 Thermal Monitor 2 79
5.3 Thermal Diode 81
PECI Host 84
Controller 84
Domain 0 84
5.4.2.1 PECI Device Address 86
5.4.2.2 PECI Command Support 86
6 Features 87
6.2.2.1 HALT Powerdown State 88
6.2.3.1 Stop Grant State 89
Features 90
6.3 Enhanced Intel 91
SpeedStep 91
Technology 91
7.1 Mechanical Specifications 94
7.2 Electrical Requirements 95
7.3 Thermal Specifications 97
7.3.2 Variable Speed Fan 99
8 Debug Tools Specifications 101
Debug Tools Specifications 102

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