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Performance Tuning

Guidelines

For best performance, a cell should be configured with a multiple of 8 DIMMs or four pairs

(although the server will execute properly with an odd number of pairs). It takes 8 DIMMs to

populate both memory buses. Populating only one of the two memory buses on a cell board

will deliver only half the peak memory bandwidth.

Load memory equally across the available cell boards.

Memory Latencies

There are two types of memory latencies within the HP 9000 rp8440 Server:

Memory latency within the cell refers to the case where an application either runs on a

partition that consists of a single cell or uses cell local memory.

Memory latency between cell refers to the case where the partition consists of two or more

cell and cell interleaved memory is used. For example, for an rp8440 server with four cells in

the partition, 25% of the addresses are to memory on the same cell as the requesting

processor, and the other 75% of the addresses are to memory on the other three cells.

The HP 9000 rp8440 Server memory latency depends on the number of processors in the

partition. Assuming that memory accesses are equally distributed across all cell boards and

memory controllers within the partition, the average idle memory latency (load to use) is as shown

below:

Number of processor modules

Average Memory Latency

4-processor

185 ns

8-processor

249 ns

16-processor

334 ns

I/O Architecture

Components within the I/O subsystem are the I/O controllers, internal peripheral bay, and

multifunction Core I/O. The figure below shows the basic block diagram of the I/O subsystem. The

Integrity I/O architecture utilizes industry standard PCI buses in a unique design for maximum

performance, scalability and reliability.

The HP 9000 rp8440 Server contains two master I/O controller chips located on the PCI X

backplane. Each I/O controller contains sixteen high performance 12 bit wide links, which connect

to sixteen slave I/O controller chips supporting the PCI X card slots and core I/O. Two links, one

from each master controller is routed through the crossbar backplane and is dedicated to core I/O.

The remaining thirty links are divided among the sixteen I/O card slots. This one card per link

architecture leads to greater I/O performance and higher availability. Each controller chip is also

directly linked to a host cell board. This means that at least two cell boards, located in cell slots 0

and 1, must be purchased in order to access all sixteen I/O card slots. With one cell board,

access to eight slots is enabled.

The HP 9000 rp8440 Server can be purchased with either one or two core I/O boards (if an SEU 2

is added, then four core I/O boards with two core I/O in the SEU 2). Both core I/O boards are

identical and provide console, SCSI, serial, and Management Processor (MP) functionality. The

second core I/O is used to enable the dual hard partitioning in the HP 9000 rp8440 Server and

provide access to a second set of disk drives.

The internal peripheral bay is divided into two identical halves. Each half supports up to two low

profile disks and one removable media device. A SCSI controller chip located on each core I/O

board supports each half of the internal peripheral bay. This means that both core I/O boards

must be purchased to access both halves of the peripheral bay.

QuickSpecs

HP 9000 rp8440 Server

Configuration

DA - 12697 U.S. QuickSpecs — Version 4 — 3/3/2008

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QuickSpecs 1

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