HP B160L Manual do Utilizador Página 11

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Overview
2.1 Overview
An overview on the multiple designs of the PA-RISC platform from the early 1980s to mid-2000s:
1. Early 32-bit systems (1980s TS-1, NS-1, NS-2 and PCX) use custom designs, with most based
on SIU/SPI main bus controllers attaching the CPU to the SMB bus. In most cases the system
processing and I/O units are made up of a large number of individual chips or boards forming the
central chipset. They use CIO and HP-PB expansion buses.
2. PA-7000 and PA-7100 systems use the ASP chipset and Viper memory controller. They utilize the
VSC CPU/memory, GSC system main and SGC and EISA expansion buses, with servers using the
HP-PB expansion bus, all provided by separate I/O adapters.
3. PA-7100LC and PA-7300LC systems use the highly integrated LASI chipset, which combines
most functions and I/O on a single chip, and an on-CPU MIOC memory controller. These system
use GSC or GSC+ as main bus and a variety of expansion buses via bus adapters, ranging from
HSC/GSC, EISA to PCI and VME. EISA is provided by Wax, PCI by Dino.
4. PA-7200, PA-8000 and some PA-8200 systems use the U2/Uturn I/O adapters, which attach two
GSC/HSC buses to the main Runway bus, and MMC/SMC memory controllers. I/O is realized
on the GSC bus with the LASI chipset and Wax and Dino I/O adapters
5. Some PA-8500, PA8600 and PA-8700 systems use a “rope” -based architecture with Astro as
main system controller and separate Runway+/Runway DDR buses with I/O devices controlled
by Elroy PCI bridges.
6. Other 64-bit midrange servers based on the same processors (PA-8500 to 8700) are based on
the Stretch chipset, a rather complicated setup with central system controller and links to sepa-
rate processor and I/O controllers and PCI bridges. Main system bus is the Itanium bus, with
converters for the processors’ Runway+/Runway DDR buses.
7. The Superdome “mainframe” and a smaller server, based on PA-8700 and PA-8800/PA-8900
are based on the Cell chipset, similar to the Stretch, but more scalable. Systems are made up
of “cells” , with their own central system/memory controller, I/O controller and PCI bridges.
8. The last PA-RISC systems (PA-8800/PA-8900) and several second-generation Itanium systems use
the HP zx1 chipset, conceptually similar to Astro systems but with higher datarates and options,
based on Itanium 2/McKinley buses.
9. Systems from the Exemplar family as the Convex SPP and HP V-Class are based on the Convex
Exemplar crossbar architecture.
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