HP B160L Manual do Utilizador Página 300

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HP Integrity rx4640 Internals
Six zx1 IOAs (I/O adapters) connect the PCI-X slots and I/O devices to the zx1 MIO with an
aggregate bandwidth of 4.0GB/s on eight 0.5GB/s channels
1. PCI-X 64/133 I/O slot on two channels 1.0GB/s
2. PCI-X 64/133 I/O slot on two channels 1.0GB/s
3. Two PCI-X 64/66 I/O slots on one channel 0.5GB/s
4. Two PCI-X 64/66 I/O slots on one channel 0.5GB/s
5. Core I/O: SCSI and Gigabit Ethernet on one channel 0.5GB/s
6. Core I/O: Management LAN, IDE, USB, serial and VGA on one channel 0.5GB/s
The I/O connectivity part of the chipset is made up of standard third-party I/O chips:
Gigabit Ethernet (Broadcom 5701)
Two-channel Ultra320 SCSI controller (LSI 53C1030)
Ultra ATA-100 IDE controller (PCI649)
EHCI USB controller
Serial controller, DUART (16550A-compatible)
“Diva” remote management processor serial and LAN
Processor Dependent Hardware (PDH) Controller
FPGA controller for ACPI (2.0) and LPC
Baseboard Management Controller for IPMI management interface (the BMC is a ARM7 RISC
processor)
Buses
Itanium 2/zx1 processor bus 6.4GB/s at 200MHz DDR
Two independent zx1 memory buses, 200MHz, each 6.4GB/s aggregate 12.8GB/s memory
bandwidth
Eight zx1 I/O channels/buses, aggregate 4.0GB/s
Two PCI-X 64/133 I/O buses
Two PCI-X 64/66 I/O buses
PCI-X 64/66 I/O bus (for SCSI/Gigabit Ethernet onboard)
PCI 32/33 I/O bus (for IDE/USB/management onboard devices)
Two SCSI-3 Ultra320 (LVD) storage I/O buses
UltraATA-100 IDE storage I/O bus
Memory
DDR200 CL2 registered ECC SDRAM DIMMs, 200MHz, 184-pin 2.5V
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