
PA-RISC Chipsets Cell
Features
Two system buses 133MHz, each 2.1GB/s peak — aggregate 4.3GB/s (these system buses are
Itanium/Merced system buses)
Up to four memory buses, each 2.1GB/s peak — aggregate 8.6GB/s bandwidth to the memory (on
the rp7400)
DEW port converters for attachment of PA-8x00 processors with Runway to the Merced system
bus — up to four DEWs were found in actual systems
I/O controllers attach to the system bus
Multiple I/O channel configurations from the IKE I/O controller(s) supported — each 133MHz
256MB/s with eight, twelve or 22 links found in actual systems (2.1GB/s, 3.2GB/s or 6.4GB/s
aggregate max bandwidth)
References
hp server rp7400 whitepaper, Hewlett-Packard Company (February 2002, product number 5981-
0154EN) [did not find an appropriate URL for this PDF document — Ed.]
rp7400 Hardware Manual
77
(PDF) Hewlett-Packard Company (May 2002)
hp server rp5400 series entry-level UNIX servers technical whitepaper, Hewlett-Packard Com-
pany (August 2002) [did not find an appropriate URL for this PDF document — Ed.]
2.4.14 Cell
Used in
N4000 (rp7405, rp7410)
Superdome
The Superdome and various smaller systems from HP used a cell-based system architecture or “Central
Electronics Complex” (CEC) which was based on interconnecting individual system/processor cells via
central crossbars. The cell boards were seated in the backplane of the system, which provided the
cell-to-cell links and I/O functionality.
1. Cell controller (CC): the central chipset and crossbar of these systems. One sits at the centre of
each cell board for a maximum of two in the complete system. The CCs provide links for:
Up to four Processors (8.0GB/s)
Up to two Memory “banks” (4.0GB/s peak)
I/O via SBA (cell to I/O communication is 2.0GB/s peak)
PDH (processor dependent hardware) and firmware/flash etc.
Second cell via XBC (cell-to-cell communication is 8.0GB/s peak)
77
http://docs.hp.com/en/3687/rp7400_customer_hardwaremanual.pdf
59
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