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PA-RISC CPU Architecture Multimedia Acceleration eXtensions (MAX-1 and MAX-2)

 An instruction which is at an odd word address and executed as a target of a taken branch is

never bundled.

 An instruction which might nullify its successor is never bundled with this successor. Only if the

successor is a FLOP instruction this bundle is allowed.

PA-7200 superscalar capabilities

This is a 2-way superscalar processor implementation. It has two integer ALUs and one FPU. Similar to

the PA-7100LC, shift-merge and test condition units are not duplicated in the second ALU. To support

the superscalar capabilities one additional write port and two additional read ports were added to the

general registers (GR*).

Allowed bundles

Table 2.6: PA-7100LC/PA-7300LC allowed instruction bundles

First (older)instruction second (younger) instruction

FLOP + LDST/ALU/MM/NUL/BV/BR

LDST + FLOP/ALU/MM/NUL/BR

ALU + FLOP/LDST/ALU/MM/NUL/BR/FSYS

MM + FLOP/LDST/ALU/FSYS

NUL + FLOP

2.3.6 Multimedia Acceleration eXtensions (MAX-1 and MAX-2)

MAX-1 (32-bit)

The original multimedia extensions were proposed for and introduced in the PA-7100LC processor and

later also available in the PA-7300LC. The aim was to enable workstations with this CPU to provide

real-time MPEG video decompression and playback at a rate of 30 frames/second without the need for

a special DSP (digital signal processing) chip.

The design process for the PA-7100LC processor (in the early mid-1990s) included for the ﬁrst time

multimedia benchmarks while analyzing optimizations for the instruction set design.

The actual implementation was achieved via the introduction of a very small set of SIMD-MIMD (See

Note 1) instructions to faciliate the application of a small set of instructions on bundled subword

data. Since these instructions use the same data paths and execution units within the processor as

the “normal” instructions the term intrinsic signal processing (ISP) was coined. By sticking to conven-

tional RISC principles the design team decided against adding complex special-purpose instructions and

opted for small, elegant use of the existing processing facilities, which just were modiﬁed to understand

the new, packed subword data.

In 1994, the extensions made their way to be included in the ﬁnal PA-7100LC product and as such were

the ﬁrst SIMD (See Note 1) instructions found in a general microprocessor. Less than 0.2 percent of

the silicon area had to be used for these additions and modiﬁcations, while allowing a very signiﬁcant

performance boost in affected applications (for example, the then-highend 735/99 workstation running

at 99 MHz with 512KB cache achieves 18.7 fps at MPEG decompression benchmarks, while the new,

lower clocked 712 workstation at 60MHz and with 64KB cache achieved 26 fps). New MAX-1 mul-

timedia instructions include: parallel add, parallel subtract, parallel shift left & add (i.e. multiply with

integer), parallel shift right & add (i.e. division), parallel average.

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