
PA-RISC Processors PA-7300LC (PCX-L2) (Velociraptor)
2.2.8 PA-7300LC (PCX-L2) (Velociraptor)
Used in
744, 745, 748
A180, A180C
B132L, B132L+, B160L, B180L+
C132L, C160L
D220, D230, D320, D330
RDI PrecisionBook
Hitachi 3050RX 255, 355E, 365
Time of introduction
Mid 1996
Overview
The PA-7300LC is the direct descendant of the PA-7100LC and likewise designed for low-cost systems.
It is still a PA-RISC 1.1 32-bit processor in contrast to the new PA-RISC 2.0 64-bit PA-8000 introduced
in the same timeframe. While the PA-7300LC is rather close to the original PA-7100LC design it has
several significant enhancements:
1. Large on-chip L1 caches, in contrast to the small “assist” caches of the 7100LC and 7200
2. Integrated L2 controller in the MIOC
3. Improved bus interface, a faster GSC
The then current process technologies made it possible to include a large L1 cache on the CPU die,
breaking a long-standing HP tradition of large off-chip L1 caches. The PA-7300LC was the final 32-
bit, PA-RISC version 1.1 CPU, later workstations and servers used 64-bit PA-RISC 2.0 processors.
PA-RISC version 1.1e 32-bit
Three functional units: 2 integer ALUs, 1 Floating Point unit (See Note 1)
2-way superscalar
MAX-1 multimedia extensions (subword arithmetic) for multimedia applications (not explicitly
mentioned on the PA7300LC, but its documentation states support for MAX-1 instructions)
64KB/64KB I/D on-chip L1 caches, each two-way set associative, virtually indexed
Cache line size of 32 Byte
Caches have a 64-bit datapath to the execution units, 256-bit datapath to main memory
Optional unified I/D L2 off-chip cache, up to 8192KB
No hashing for both I and D caches
L2 cache is write-through, direct mapped, physically indexed and physically tagged
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