HP B160L Manual do Utilizador Página 33

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PA-RISC Processors PA-8700 (PCX-W2) (Piranha)
SMP-capable
External memory and I/O controllers
160-entry fully-associative dual-ported TLB
32-entry BTAC (branch target address cache)
2048-entry BHT (branch history table)
Dynamic and static branch prediction modes
On-chip L1 caches 0.5MB I and 1MB D, each 4-way set associatve
32 or 64 Byte cache line size
Supports up to 1 TB of physically addressable memory (40-bit physical addresses)
56-entry instruction queue/reorder buffer (IRB)
MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG
decoding
Quasi LRU replacement policy for the instruction cache
Bi-endian support
Runway+/Runway DDR system/memory bus, 125MHz, 64-bit, DDR (double data rate), about
2.0GB/s peak bandwidth
CPU interfaces in smaller systems to the Astro memory and I/O controller, in larger/mainframe
systems to the DEW Runway ports/converters of the Stretch chipset or to the Cell chipset (prob-
ably with converters, since Cell is also an Itanium chipset)
Up to about 550MHz frequency with 2.0V core voltage
21.3×22.0 mm
2
die, 140,000,000 FETs, 0.25µ(micron), 5-layer metal CMOS packaged in a 544-
pin LGA package
2.2.13 PA-8700 (PCX-W2) (Piranha)
Used in
A400-6X (rp2430), A500-6X, A500-7X (rp2470)
C3650, C3700, C3750
J6700
L1500-6X, L1500-7X, L1500-8X (rp5430), L3000-6X, L3000-7X, L3000-8X (rp5470)
N4000-6X, N4000-7X (rp7400)
N4000-6X, N4000-7X, N4000-8X (rp7405, rp7410)
Superdome
Time of introduction
August 2001
26
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