
PA-RISC Processors PA-8000 (PCX-U) (Onyx)
Instruction prefetch buffer moved from memory controller to L1 instruction cache, thus allowing
prefetch hits without penalty
On-chip MIOC memory controller
96-entry unified I/D TLB
8-entry BTLB
4-entry ILAB
GSC system interface (implements GSC+ features), maximum clock frequency of 40MHz — actual
system implement from 33MHz (132MB/s), 36MHz (140MB/s) and up to 40MHz (160MB/s)
Either 64-bit or 128-bit datapath from execution units to the memory
Up to 180MHz frequency with 3.3V core voltage
15.3×17.0 mm
2
die, 9,200,000 FETs, 0.5µ(micron), 4-layer metal CMOS (CMOS14C process)
packaged in a 464-pin ceramic PGA package
Notes
1. Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with
simple math operations, like integer addition o multiplication. Both units can handle branch operations.
References
PA7300LC ERS (External Reference Specification)
18
(PDF, 716KB) Hewlett-Packard Company
(1996).
The PA-7300LC: the first “System on a Chip”
19
(archive.org mirror) Tom Meyer (1996: Presen-
tation for Microprocessor Forum 1995).
The PA 7300LC Microprocessor: A Highly Integrated System on a Chip
20
(PDF, 50KB). Terry W.
Blanchard and Paul G. Tobin (June 1997: Hewlett-Packard Journal).
2.2.9 PA-8000 (PCX-U) (Onyx)
Used in
C160, C180
D270, D280, D370, D380
J280, J282
K250, K260, K450, K460
R380
T600
HP/Convex SPP2000 (S-Class/X-Class)
18
http://ftp.parisc-linux.org/docs/chips/pcxl2_ers.pdf
19
http://web.archive.org/web/20040214111649/http://www.cpus.hp.com/technical_references/101995wp.shtml
20
http://ftp.parisc-linux.org/docs/whitepapers/pa7300lc_on_chip.pdf
19
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