
PA-RISC Processors Hitachi HARP-1
Details
PA-RISC version 1.1 32-bit
Built-in, pipelined FPU
L1 I: 8KB, 2-way set-associative, 32-byte blocks
L1 D: 4KB, 2-way set-associative, 32-byte blocks, copy-back
L1 caches are on-chip
Uncacheable memory (per page)
TLB: I/D 32/64-entry, 2-way set, 4K-page, each +2 additional block entries
BTLB (256KB-32MB)
Seven 32-bit shadow registers for fast interrupts
Data-prefetching
Non-blocking cache
Power-saving mode, reducing frequency to 1/8
Support for SDRAM
PA/50L: Up to 33MHz frequency with 3.3V core voltage
PA/50M: Up to 60MHz frequency with 5.0V core voltage
11.5×12.0 mm
2
die, 1,280,000 FETs, 0.6µ(micron), 3-layer metal CMOS packaged in a 160-pin
plastic QFP package
References
PROgress (PA-RISC) Newsletter - comp.sys.hp
34
Candace Doyle (October 1993: Precision Risc
Organization. Accessed December 2007)
2.2.17 Hitachi HARP-1
Used in
Hitachi SR2201 supercomputer (HARP-1E)
Probably others
Time of introduction
June 1994
34
http://groups.google.com/group/comp.sys.hp/msg/32de7bed6bae1c42
32
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