HP B160L Manual do Utilizador Página 60

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PA-RISC Chipsets Viper
Two CCUs (cache controller units CCU0 and CCU1) for the cache access
Physical address space of 29-bit (512MB main memory could be addressed)
Memory is attached to the SMB main bus
I/O is attached to the SMB main bus (with two 32-bit converters over the CTB)
Cache is attached to the CCUs which attach to the CPU
NS-2:
SIU (system interface unit) for the system and memory bus
Two CCUs (cache controller units, split into instruction and data ICCU and DCCU)
Physical address space of 29-bit (512MB main memory could be addressed)
Memory is attached to the SMB main bus
I/O is attached to the SMB main bus (with two 32-bit converters over the CTB)
Cache is attached to the CCUs which attach to the CPU
PCX:
SPI (SMB to processor interface)
Three CMUX (cache multiplexer one instruction, two data)
Physical address space of 29-bit (512MB main memory could be addressed)
Memory is attached to the SMB main bus
I/O is attached to the SMB main bus (with two 32-bit converters over the CTB)
Cache is attached to the CMUXs which attach to the CPU
2.4.8 Viper
Viper is the external single external memory and I/O controller (MIOC) on systems with PA-7000 and
PA-7100 processors. The chip is apparently similar on both, and sometimes counted into the ASP I/O
chipset.
Viper interfaces with PBus to the processor and VSC to the system main bus. It handles all memory
and I/O traffic between the processor and the rest of the system.
Bus attachments
Viper attaches with 32-bit multiplexed address/data bus (PBus) to the CPU
Memory attaches directly to Viper, with multiplexed 64-bit ECC
VSC system main bus attaches to Viper (32-bit on PA-7000, 64-bit on PA-7100)
System main bus interface via two custom ASICs (system bus interface SBI)
I/O attaches with bus adapters to VSC bus
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