
PA-RISC Processors PA-7200 (PCX-T’) (Thunderbird’)
References
1. PA7100LC ERS (External Reference Specification)
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(.pdf) Hewlett-Packard Company (1999)
2. The PA 7100LC Microprocessor: A Case Study of IC Design Decisions in a Competitive Envi-
ronment
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Mick Bass et al (April 1995: Hewlett-Packard Journal. Accessed May 2009)
3. Design methodologies for the PA 7100LC microprocessor
15
(.pdf) Mick Bass et al (April 1995:
Hewlett-Packard Journal. Accessed May 2009)
2.2.7 PA-7200 (PCX-T’) (Thunderbird’)
Used in
C100, C110
D250, D260, D350, D360
J200, J210
K100, K200, K210, K220, K400, K410, K420
Convex SPP1200/CD, SPP1200/XA, SPP1600/CD, SPP1600/XA
Hitachi 9000V VQ200, VQ210, VR100, VR200, VR400
Time of introduction
Early 1995
Overview
The PA-7200 completely revised the PA-7100 processor core, leveraging only the FPU. Being a two-way
superscalar processor, the PA-7200 can dispatch and execute two separate instructions at a time to its
functional units. In contrast to the PA-7100 it has two separate integer ALUs and thus can execute
two ALU integer operations simultaneously. Other changes include a redesigned cache architecture
— while retaining the general cache layout with large off-chip L1 caches at CPU clock speed — and
use of the Runway processor bus, carried on to later PA-8x00 processors. The PA-7200 was targeted
towards high-performance general-purpose applications, but also on specialized applications with large
working sets which could take advantage of the high-bandwidth bus interface.
Details
PA-RISC version 1.1d 32-bit
Three functional units: 2 integer ALUs, 1 Floating Point
2-way superscalar
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http://ftp.parisc-linux.org/docs/chips/PCXL_ers.pdf
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http://www.hpl.hp.com/hpjournal/95apr/apr95a2.pdf
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http://www.hpl.hp.com/hpjournal/95apr/apr95a3.pdf
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