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PA-RISC CPU Architecture

2.3 PA-RISC CPU Architecture

2.3.1 PA-RISC overview

PA-RISC was HP’s take on RISC and the 1980s offspring of previous design efforts and lessons that

learned from developing the FOCUS CPU. The PA-RISC processors were designed to replace the

16-bit stack-based CPUs in HP 3000 servers and Motorola 680x0 CPUs in HP’s Unix systems, and

unify all commercial products onto a common system architecture. At the time of development RISC

(Reduced Instruction Set Computing) platforms were largely expected to replace the CISC architectures,

with well known examples as Intel x86, Motorola 68k.

Overall PA-RISC was a rather conservative RISC design:

 The instruction set is implemented in hardware and not microcoded, as for in example in conven-

tional CISCs (or HP FOCUS).

 The instruction size has a ﬁxed length — one word (32-bit).

 Only three addressing modes: long/short displacement and indexed mode.

 Only load/store operation access the memory, no computational instructions directly access the

memory.

 The PA-RISC instruction set was designed to be a good target for optimizing compilers. Many

simple, frequently used instructions execute in just one cycle, more complex computation were

assigned to assist processors or software algorithms.

Compared to other RISC architectures from the time the original PA-RISC design was rather unspectac-

ular — it had typically fewer features but remained always at competitive speeds, especially in Floating

Point and SMP (multiprocessing) areas. HP was the ﬁrst to include multimedia extension in a com-

mercially available microprocessor (MAX-1 in the PA-7100LC and MAX-2 64-bit in the PA-8000

— similar to Intel’s MMX et al.) which allowed vector operations on two or four 16-bit subwords in

32-bit or 64-bit integer registers.

The original PA-RISC 1.0 architecture included a single instruction/data bus; PA-RISC later on moved

to a Harvard-style architecture with seperate instruction and data buses. It has thirty-two 32-bit in-

teger general purpose registers (GR0-GR31), seven shadow registers (SR0-SR6) for fast-interrupts and

thirty-two 64-bit Floating Point registers for the FPU, which also could be combined to 64×32-bit and

16×128-bit. The FPU is able to execute a Floating Point instruction simultaneously to the ALU. The

original addressing was 48-bit wide, it was later on expanded to 64-bit (with the introduction of the

PA-8000 line). (See Note 1)

The PA-RISC architecture was extended to version 1.1 with the PA-7000 processor in 1991. The major

change in PA-RISC 1.1 was the inclusion of a MMU (memory management unit), that enables the

PA-RISC platform to use virtual memory. From the the second PA-RISC 1.1 processor, the PA-7100,

onward all processors implement superscalar instruction execution — the ability to execute multiple

instructions simultaneously. The 32-bit variants are up to two-way superscalar, later 64-bit processors

up to four-way. Other signiﬁcant developments include the PA-7100LC and PA-7300LC (LC for low

cost) processors, which integrate the memory and I/O controller onto the processor die (on the PA-

7300LC additionally the cache controller and ﬁrst-level cache).

In 1996 the 64-bit redesign of the PA-RISC architecture was introduced with the PA-RISC 2.0 PA-

8000 processor. The architectural changes were rather intrusive, while staying compatible with the

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