
PA-RISC Processors PA-8600 (PCX-W+) (Landshark)
A 500 MHz 1.5 MByte Cache with On-Chip CPU
27
(PDF, 141KB) Jonathan Lachman and J.
Michael Hill (1997: ISSCC).
PA-8500: The Continuing Evolution of the PA-8000 Family
28
(archive.org mirror) Gregg Lesartre
and Doug Hunt (1997: Proceedings of CompCon, IEEE CS Press). [Article reprint for vanished
cpu.hp.com]
2.2.12 PA-8600 (PCX-W+) (Landshark)
Used in
A400-5X (rp2400), A500-5X (rp2450)
B2000 (some), B2600
C3600
J5600, J6000, J7600
L1000-5X (rp5400), L2000-5X (rp5450)
L1500-5X (rp5430), L3000-5X (rp5470)
N4000-5X (rp7400)
V2600
Superdome
Stratus Continuum 439, 449, 651-2, 652-2, 1251-2, 1252-2
Time of introduction
January 2000
Overview
The PA-8600 is a PA-8500 with minor modifications for a new manufacturing process in order to
achieve higher clock speeds, which was the main aim of developing the PA-8600. One of the few
changes to the original design is a quasi LRU replacement policy for the instruction cache.
Details
PA-RISC version 2.0 64-bit
Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2
Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
4-way superscalar
Two address adders
27
http://ftp.parisc-linux.org/docs/whitepapers/isscc_cache_talk.pdf
28
http://web.archive.org/web/20040214131135/http://www.cpus.hp.com/technical_references/8500.shtml
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