HP B160L Manual do Utilizador Página 54

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PA-RISC Chipsets ASP
Intel 8042 microprocessor controlling:
Battery backed RTC
System & user timers
Audio generator
HP-HIL interface
Frontpanel system status LEDs
25-33MHz clock frequency
160-pin QFP chip (ASP)
ASP2 additional features
NCR 53C720 16-bit Fast-Wide differential SCSI-2
ASP2: AMD Formac Plus Am79C830 FDDI controller (ASP2)
ASP2: Stereo/CD quality audio
Two 32-bit device data buses (these are some variant of GSC bus)
1. bus attaches to LAN an FDDI
2. bus attaches to the two SCSI controllers, audio and via an 8-bit bus converter to the other
I/O devices (serial, parallel, etc.)
ASP2 consists of two separate chips (IOSS):
1. Shortstop is the main data attachment to the VSC system main bus (and Viper memory con-
troller) with 33MHz clock speed, produced in 0.8µ(micron) in CMOS (CMOS26B) pack-
aged in 160-pin PLCC
2. Cutoff is the main address controller with 33MHz clock speed, produced in 0.8µ(micron) in
CMOS (CMOS26B) packaged in 240-pin PQFP
EISA bridges
Most systems with an ASP chipset feature a separate EISA bus, implemented with the Intel 82350
chipset (82352 EISA buffer, 82357 peripheral and 82358 controller). The EISA adapter is not integrated
into or part of ASP but listed here since this configuration was only used with ASP systems.
References
1. Midrange PA-RISC Workstations with Price/Performance Leadership
54
(.pdf) Andrew J. DeBaets
and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal) pp. 6-11
2. VLSI Circuits for Low-End and Midrange PA-RISC Computers
55
(.pdf) Craig A. Gleason (August
1992: Hewlett-Packard Journal) pp. 12-22
54
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1992-08.pdf
55
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1992-08.pdf
47
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