
PA-RISC Processors Hitachi PA/50
0.75MB I and 0.75MB D on-chip L1 caches per core
64MB off-chip L2 cache, four-way associative, physically indexed and tagged
ECC for L2 data and tags
MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG
decoding
Itanium 2/McKinley processor bus, 200MHz clock ( “double-pumped” ), 128-bit datapath, 6.4GB/s
bandwidth, data ECC-protected, signals parity
CPU interfaces to the Cell chipset or the zx1 chipset’s MIO
44 bit physical addressing
64 bit virtual addressing
Four GB maximum page size
Up to 1.1 GHz frequency
23.6×15.5 mm
2
die, 317,000,000 FETs, 0.13µ(micron), 8-layer Silicon-on-Insulator CMOS (ap-
parently fabbed by IBM)
References
Overview of the HP 9000 rp3410-2, rp3440-4, rp4410-4, and rp4440-8 Servers
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(PDF, 700KB)
Hewlett-Packard (2005).
2.2.16 Hitachi PA/50
Used in
Hitachi 3050RX 100C, 200
Time of introduction
About 1993
Overview
The PA/50 is a PA-RISC version 1.1 compatible processor designed and manufactured by Hitachi. Two
designs were developed: M and L (L for low-cost). They were used as personal workstation processors
and high-end embedded controllers. Hitachi integrated a set of features previously not implemented
at that time in other PA-RISC processors, e.g., on-chip caches, data-prefetching, a power-saving mode
and SDRAM support.
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http://h71028.www7.hp.com/ERC/downloads/5982-4172EN.pdf
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