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PA-RISC Processors Other processors

 W90210F PA-RISC Embedded Controller

(.pdf) Winbond Electronics Corp. (October 1997.

Accessed January 2008)

Winbond W90220 and W90221

Time of introduction: Spring 1999

The W90220F is, as its predecessor W90210, a 32-bit PA-RISC 1.1 design without MMU but integrated

many external I/O components on the chip — DRAM and DMA controllers, PCI bridge, IDE channels,

I/O ports and, on the W90221, a graphics/TV chip. It had the same target systems of set-top boxes and

internet appliances. The sucessor W90221 is apparently similar, with higher clock speed, integrated

(S)VGA and TV controller

 PA-RISC version 1.1 (third edition) 32-bit

 Level 0 implementation (no virtual addressing): no MMU

 Six-stage pipeline

 Two functional units: one 32-bit integer ALU and one 32-bit multiply-accumulate (MAC) module

(for DSP purposes, can be used as two 16-bit modules too)

 L1 I cache: 4KB, direct mapped, 32-byte blocks, 256 entries

 L1 D cache: 4KB, 4-way set-associative, write-back or write-through

 MAX-1 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG

decoding

 80486 (Intel) bus interface

 Hardware dynamic branch prediction

 256-entry branch-target-buffer (i. e. BTAC)

 Memory controller (supports DRAM, EDO-DRAM and SRAM; W90221 additionally SDRAM)

 ROM/FLASH interface

 DMA controller (2-channel 8-bit)

 IDE I/O controller (four 16-bit channels)

 W90221: VGA and TV controller (W9971)

 PCI bridge

 Two serial ports

 Parallel port

 Serial ICE port

 Up to 150MHz clock speed at 3.3V/5V I/O and 3.3V core

 W90221: 133MHz clock speed with apparently 3.3V at both I/O and core

 0.35µ(micron) single-poly-triple-metal CMOS

 208-pin PQF package

http://www.datasheetarchive.com/pdf/3656144.pdf

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