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PA-RISC Processors Early PA-RISC

NS-2

Used in: 822, 832, 845, 855, 860

Introduced in: 1989-1990

The ﬁnal NMOS PA-RISC processor was the NS-2, a tweaked follow-on to the NS-1 with increased

pipeline stages (from three to ﬁve), new TLB and cache controllers and signiﬁcantly larger caches and

TLB. The NS-2 design was simpliﬁed over its NS-1 predecessor. The processor is implemented on

one circuit board with the CPU as a single NMOS-III and seven other VLSI chips. The bus structure

connecting these chips was updated and simpliﬁed, with the CPU having private connections to the

cache and TLB controllers (for which the NS-1 CPU had to use the shared cache bus).

Details:

 PA-RISC version 1.0 32-bit

 CPU is a single chip with seven VLSI support chips

1. SIU (system interface unit), attaches the CPU to the SMB main bus

2. two CCUs (cache controller units, split into instruction and data — ICCU and DCCU), at-

tach to separate external cache chips

3. TCU (TLB controller unit), attaches to the external TLB chips

4. FPC (ﬂoating point controller), controls two third-party ﬂoating point (FP) chips (ADD,

MULTI)

 Five-stage pipeline

 16384-entry TLB off-chip

 Off-chip L1 cache up to 1024KB, split into I/D

 Physical address space of 29-bit (512MB main memory could be addressed)

 CPU attaches via System Main Bus (SMB) to memory and I/O (controllers)

SMB is a synchronous, pipelined bus with 64-bit wide address and data transfers

 27.5MHz clock speed (or maximum of 30MHz?), power dissipation of 26W

 One circuit board, CPU implemented in NMOS-III, 183,000 FETs, 1.5µNMOS-III, die size 14.0×14.0

die, packaged in 408-pin PGA

PCX (CMOS26B)

Used in: 842, 852, 865, 870

Introduced in: 1990?

The last PA-RISC 1.0 design was the CMOS26B or PCX and the ﬁrst PA-RISC processor fabricated in

a CMOS process. It implemented the NS-1/NS-2 NMOS design and several of the processor functions

previously supplied on external VLSI chips onto a single CPU chip. The PCX still was supplemented by

external support chips, including three CMUX (cache multiplexer — one instruction, two data; equiva-

lent to the earlier CCUs), SPI (SMB to processor interface — SMB is the system main bus), FPC (ﬂoating

point coprocessor) and two FP chips (MUL/DIV and ADD/SUB) [not completely clear if the latter two

or latter three chips are third-party].

 PA-RISC version 1.0 32-bit

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