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PA-RISC CPU Architecture Superscalar execution

PA-7100 superscalar capabilities

The PA-7100 is two-way superscalar with one integer ALU and one FPU.

Allowed bundles

Table 2.4: PA-7100 allowed instruction bundles

First (older)instruction Second (younger) instruction

ALU + FLOP

LDST + FLOP

FLOP + ALU/LDST/Branch

PA-7100LC/PA-7300LC superscalar capabilities

These are 2-way superscalar processor implementations with two integer ALUs and one FPU. Notably

only one of the two ALUs is capable to handle loads, stores and shifts.

Allowed bundles

Table 2.5: PA-7100LC/PA-7300LC allowed instruction bundles

First (older)instruction Second (younger) instruction

FLOP + LDST/ALU/MM/NUL/BV/BR

LDST + FLOP/ALU/MM/NUL/BR

ALU + FLOP/LDST/ALU/MM/NUL/BR/FSYS

MM + FLOP/LDST/ALU/FSYS

NUL + FLOP

SYS Never bundled

Besides from these bundles, LDST + LDST bundles are under certain circumstances also possible. These

are then called double word load/store.

Data dependencies

Several kinds of instructions cannot be bundled together because of inter-instruction data dependencies:

 An instruction that modiﬁes a register will not be bundled with another instruction that takes this

Exception: a FLOP can be bundled with a FP store of the FLOP’s result register.

 A FP load to one word of a doubleword register will not be bundled with a FLOP that uses the

other doubleword of this register.

 A FLOP will not be bundled with a FP load if both instructions have the same target register.

 An instruction that could set the carry/borrow bits will not be bundled with an instruction that

uses carry/borrow bits.

Control Flow

 An instruction which is in the delay slot of a branch is never bundled with other instructions.

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HP B160L Manual do Utilizador Página 49