HP B160L Manual do Utilizador Página 72

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PA-RISC Buses System Main Bus (SMB)
Separate data and address buses
Memory data blocks are transferred in 16, 32 or 64 Byte blocks
Provides cache and TLB coherency on multi-processor configurations as a snoopy bus
Various clock speeds were supported, as a ratio of the processor clock speed (2/3 was common
[or maybe the maximum Ed.])
Maximum data rate depends on clock speed and bus width, with common 60MHz and 64-bit:
480MB/s
Apparently 3.0V signalling voltage
References
1. Corporate Business Servers: An Alternative to Mainframes for Business Computing
83
(.pdf)
Thomas B. Alexander et al (June 1994: Hewlett-Packard Journal)
2.5.7 System Main Bus (SMB)
In early PA-RISC (1.0) systems with the NS-1, NS-2 and PCX processors the CPU attaches via bus
converters to the System Main Bus.
Bus features
64-bit data width
Clockspeed of maximum 25-30MHz
Central system bus between CPU/bus adapter, memory and I/O buses
CPU attachment
1. System controllers (SIU or SPI) attach the CPU with its execution units to the SMB system main
bus
2. System Main Bus (SMB) is the central bus, to which CPU, memory and I/O buses attach
CPU attaches via SIU/SPU to SMB with 64-bit at 25-30MHz
Memory attaches to SMB
(Some) Memory extensions attach to SMB (via MABs; see below)
3. Central Bus/Midbus (CTB) attaches the I/O via bus convertes to SMB
Attaches via 32-bit at maximum of 10MHz at SMB
Two CTBs per SMB
4. CIO buses (up to three) attach via adapters to CTB
Attaches via 16-bit at 4MHz (probably dependant on CTB clock)
83
http://www.hpl.hp.com/hpjournal/94jun/jun94a1.pdf
65
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