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PA-RISC Buses PBus

 I/O expansion cards plug into CIO slots

5. (Some systems only) Memory Array Buses (MABs) attach to SMB for more memory

 Attaches via 72-bit (ECC) at SMB

The TS-1, the ﬁrst PA-RISC processor used a simpler version of this setup and directly attached the CPU

to the Central Bus (CTB) with 32-bit at 8MHz. Here, all the CPU, memory and I/O devices directly

connect to the CTB.

2.5.8 PBus

Systems with PA-7000 or PA-7100/PA-7150 processors use the PBus processor bus between the CPU

itself and the external memory controller (Viper). These system with VSC main bus mostly used ASP

chipsets. On multi-processor systems with a PA-7100, two attachment variants were possible — either

with a shared memory controller (two processors) or with a shared system bus (up to eight processors).

Bus features

 32-bit multiplexed address/data bus

 Runs at ﬁxed fractions of CPU clock (1.0, .67 and .50 of processor speed)

 Two multiprocessor strategies supported (only PA-7100; see below)

CPU attachment

1. PBus is the main processor and memory bus

 CPU attaches to PBus with 32-bit

2. Viper, the main memory and I/O controller attaches to PBus

 Memory attaches to MIOC via 72-bit (64-bit with ECC)

3. VSC, the system main bus, attaches to MIOC and various I/O controllers

 Attaches via 32-bit (PA-7000) or 64-bit (PA-7100) at MIOC

4. I/O adapters attach to VSC

 Either ASP chipset for SGC or GSC bus systems, or HP-PB adapters for some servers

Multiprocessor attachment

1. Two-way SMP ( “Low Cost” ): Two CPUs share a PBus and attach to the same MIOC. Memory

attaches directly to MIOC, I/O attaches via VSC to MIOC.

2. Scalable MP: Each CPU has its own MIOC. All MIOCs in the system share a VSC bus, to which

I/O and memory attach.

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HP B160L Manual do Utilizador Página 73