
HP N4000 (rp7400)
4.35 HP N4000 (rp7400)
4.35.1 Overview
The rp7400 were the original version of the N4000 line of servers — the newer rp7405 and rp7410
servers were also labeled as N4000 and feature a similar set of I/O options and expandability in ba-
sically the same chassis. However the original N4000, the rp7400 described here, is based around
a different system architecture than their sucessors — the Stretch chipset, also used in the L1500 and
L3000 (rp5430/rp5470) servers.
The original N4000s were shipped in two models, with differences in their system board — A3639A
and A3639B. The N4000 which was later renamed to rp7400 was shipped with an even different
mainboard and had the model number A3639C.
Introduced: 1999-2001
Model numbers: all the N4000-36, N4000-44, N4000-5X, N4000-6X and N4000-7X have the rp7400
model number.
4.35.2 Internals
CPU
The rp7400 N4000 supports one to eight processors.
The original N4000 (A3639A and A3639B) and later rp7400 (A3639C) are in fact different products,
based on the same basic architecture but with slight differences, especially relating to the type and
number of processors. Not all early N4000s support the later processors and a maximum number of
CPUs.
Processor types are indicated with the following suffixes:
-36: PA-8500 360MHz with 512/1024KB on-chip I/D L1 cache each [A3639A, A3639B, A3639C,
A8327A]
-44: PA-8500 440MHz with 512/1024KB on-chip I/D L1 cache each [A3639A, A3639B, A3639C,
A8327A]
-5X: PA-8600 550MHz with 512/1024KB on-chip I/D L1 cache each [A3639B, A3639C, A8327A]
-6X: PA-8700 650MHz with 768/1536KB on-chip I/D L1 cache each [A3639C, A8327A]
-7X: PA-8700 750MHz with 768/1536KB on-chip I/D L1 cache each [A3639C, A8327A]
Itanium 2/IA64 processors were planned on the N4000 but apparently never offered.
Chipset
The rp7400 system is based on the Stretch central electronic complex chipset, used in the L1500 and
L3000 (rp5430/rp5470) servers as well. Stretch has four main components, to which the processing
and I/O parts of the N4000 attach:
1. Prelude SMC memory controller is the central part of the system, it connects the memory to two
system buses, to which each one IKE I/O controller and two DEW Runway ports (for each two
CPUs) attach (Prelude is also called “Very Low Latency Memory Controller” )
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