HP B160L Manual do Utilizador descarregar pdf (Página 22)

PA-RISC Processors PA-7100LC (PCX-L) (Hummingbird)

 Not SMP-capable

 Five-stage pipeline

 DRAM memory & cache controller (MIOC) integrated on die, thus direct interface from the CPU

to memory and cache

 1KB on-chip I L1 instruction cache, direct mapped, 64-bit per access, prefetch from off-chip I

cache

 8KB-2MB off-chip uniﬁed I/D L1 cache, direct mapped, hashed address, virtual index, 480-

600MB/s bandwidth

 The 1KB on-chip I cache is not really considered a true cache, thus the off-chip cache in fact is

the system’s real L1 cache

 32-Byte cache line size

 Support for bi-endian load-store operations

 MAX-1 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG

decoding

 Floating Point load-store to I/O space

 64-entry uniﬁed I/D TLB, fully associative, 4K page size

 8-entry BTLB, page sizes from 512K - 64M

 64-bit wide load/store operations

 I and D cache bypassing

 Stall on use D cache miss policy

 Don’t ﬁll on miss cache hint

 Hardware TLB miss handler support

 Hardware static branch prediction

 GSC bus interface

 64-bit ECC interface to the main memory

 Instruction line prefetch from main memory

 Up to 100MHz clock

 14.2×14.2 mm

die, 900,000 FETs, 0.75µ(micron), 3-layer aluminium process packaged in a

432-pin PGA

Notes

1. Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with

simple math operations, like integer addition or multiplication. Both units can handle branch operations.

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HP B160L Manual do Utilizador Página 22