HP B160L Manual do Utilizador descarregar pdf (Página 46)

PA-RISC CPU Architecture Floating Point Unit (FPU)

32-bit PA-RISC 1.1. (On a sidenode, the PA-8000 was introduced before the last 32-bit processor

— the PA-7300LC — shipped.) Main changes in PA-RISC 2.0 include:

 All registers and functional units have been extended to 64-bit

 Virtual address space is 64-bit

 Physical address space is 40-bit on PA-8000 to PA-8600 (1TB of addressable physical memory)

and 44-bit (16TB memory) on PA-8700 and later

 Out-of-Order (OoO) execution capability with the IRB (Instruction Reorder Buffer), which stores

up to 28 computation and 28 load/store instructions and reorders and prepares the for execution

on the ﬂy. It tracks interdependecies and branch prediction outcomes as well. The IRB is the key

part in the OoO execution capability of PA-RISC 2.0.

 FPMAC (Floating Point Multiply Accumulate) units

The later PA-8x00 processors did not introduce other signiﬁcant changes besides higher integration,

such as large L1 caches in the PA-8600 and the dual-core PA-8800 and PA-8900. In fact all processors

after the PA-8000 were only redesigns and extensions of that processor core.

From the mid-1990s on a parallel track to PA-RISC 2.0 development HP joined Intel in developing the

VLIW Itanium architecture from its own R&D projects (called EPIC), which resulted in the Intel/HP

IA64 architecture. Since the early-2000s HP sold two lines of Unix computers and servers in parallel

— both PA-RISC 2.0 and Itanium.

Notes

1. Great Microprocessors of the Past and Present

, John Bayko (June 2001/V 12.1.1: BURKS. Accessed 28 Dec 2007)

2.3.2 Floating Point Unit (FPU)

The Floating Point Unit is an assist processor logically added to a system to improve the performance

on ﬂoating-point operations. The processor can be on a seperate chip (e.g., PA-7000) or integrated onto

the central CPU die (all PA-RISC CPUs upwards). The FPU executes special ﬂoating point instruction

to perform arithmetic on its own set of independent registers (register ﬁle) and to move data between

its own registers and the system’s lower memory hierarchy. The FPU execution stage is pipelined. All

PA-RISC FPUs contain thirty-two 64-bit registers, which can also be used as sixty-four 32-bit registers

and sixteen 128-bit registers.

2.3.3 Transition Lookaside Buffer (TLB)

The Translation Lookaside Buffer is a hardware structure doing virtual-to-physical memory address

translations. The TLB takes virtual page numbers and returns the corresponding physical page number.

The PA-7000 is the last PA-RISC processor to use seperate I/D TLBs, all later PA 1.1 and 2.0 CPUs use

a combined TLB structure.

 PA-7000 - 96 I and 96 D entries

 PA-7100 - 120 combined entries

 PA-7100LC - 64 combined entries

http://burks.brighton.ac.uk/burks/pcinfo/hardware/cpu.htm

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 366 367

Sem comentários

HP B160L Manual do Utilizador Página 46