HP B160L Manual do Utilizador Página 14

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PA-RISC Processors Early PA-RISC
Hitachi
PA/50
PA 1.1
32-bit
60MHz 1.28M 8KB I
4KB D
on-chip
? 1-
way?
No? 1 Integer
1 Floating Point
Hitachi
HARP-1
PA 1.1
32-bit
150MHz 2.8M 8KB I
16KB D
on-chip
512KB I
512KB D
off-chip
? 2-way No? 2 Integer
1 Floating Point
(Vector)
Table Notes
ISA: Instruction set architecture version of the PA-RISC architecture and its width, i.e. integer register width and
maximum addressable memory (32-bit or 64-bit)
FETs: Number of transistors
L1/L2 Caches: Maximum amount of Level 1 and Level 2 cache memories on-chip is integrated onto the CPU die
while off-chip cache is implemented with separate chips (most PA-RISC processors supported larger off-chip caches
than were implemented in actual products)
Bus: Type of bus the processor attaches to on the main board (note that this is in two cases the main I/O bus [GSC on
the LC processors] and on the others the processor/memory bus)
SMP: Capability of the CPU to work in multi-processor configuration
Units: Number of functional processing units, for integer and floating point arithmetic, and load/store operations.
Also notes if the MAX multimedia extensions are available.
2.2.3 Early PA-RISC
The first PA-RISC processors, designed and used in the mid to late-1980s in the HP 9000/800 servers
(and HP 3000 MPE/iX systems), are very poorly documented. Their exact nomenclatura is not clear,
one group of sources refers to them as TS-1, NS-1 and NS-2, while other call apparently the same
processors PN-5, PN-7 and PN-10. These early CPUs still mostly were chipsets multiple separate
chips and components formed the central processing unit, contrary to the mostly single-chip post-PA-
7000 implementations. The chips were based first on TTL, then NMOS-III and finally CMOS26B. An
interesting aspect of these CPUs are their huge TLB sizes from 2048 up to 16384 entries while their
successors and competitors had sizes typically in the low to mid hundreds.
TS-1
Used in: 840
Introduced in: 1986
The TS-1 was the very first PA-RISC production processor and integrated version 1.0 of PA-RISC on
six boards (each 8.4×11.3 ) of TTL.
Details:
PA-RISC version 1.0 32-bit
Three-stage pipeline
The CPU consists of six separate boards:
1. I-unit: the Instruction Unit
2. Register File Board, contains general and control registers
3. E-unit: the Execution Unit
7
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