
PA-RISC Processors Early PA-RISC
First multi-processor-capable PA-RISC CPU (up to four-way SMP)
Direct predecessor of the PA-7000 (PCXS) processor which integrated most processor logic minus
the FPU onto a single die/chip
External FPU (apparently ECL logic)
8192-entry TLB on-chip
Off-chip L1 cache up to 1024KB, split into I/D (apparently asymmetrical 1:2 I/D)
Physical address space of 29-bit (512MB main memory could be addressed)
CPU attaches via System Main Bus (SMB) to memory and I/O (controllers)
SMB is a synchronous, pipelined bus with 64-bit wide address and data transfers
50MHz clock speed
One circuit board, 196,000 FETs, 1.0µ(micron), implemented in three-level CMOS (CMOS26B)
CPU is a single chip, needs seven other (VLSI) support chips for memory/bus interfaces and I/O
There are sources which also mention a “CS-1” processor — from the nomenclatura this would point
to a CMOS design but the performance figures/charts do not really match up with the CMOS26B/PCX
described here.
References
1. Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architec-
ture (January 1988: Software Research Northwest Inc.)
2. Hardware Design of the First HP Precision Architecture Computers
1
(PDF) David A. Fotland et
al (March 1987: Hewlett-Packard Journal)
3. HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook
2
(PDF) Hewlett-Packard
Company (October 1990. Accessed January 2008 at hpmuseum.net)
4. HP 9000 Series 800 Model 825S Hardware Technical Data
3
(PDF) Hewlett-Packard Company
(September 1988. Accessed January 2008 at hpmuseum.net)
5. HP 3000/925 and HP 9000/825/835 Computer Systems CE Handbook
4
(PDF) Hewlett-Packard
Company (May 1988. Accessed January 2008 at hpmuseum.net)
6. New midrange members of the Hewlett-Packard Precision Architecture Computer Family
5
Thomas
O. Meyer et al (June 1989: Hewlett Packard Journal. Accessed January 2008 at findarticles.com)
7. HP 9000 Series 800 Model 822S/832S Technical Data
6
(PDF) Hewlett-Packard Company (1989.
Accessed January 2008 at hpmuseum.net)
8. A 30 MIPS VLSI CPU, Brian D. Boschma et al (ISSCC 89: February 1989)
1
http://hpmuseum.net/document.php?catfile=372
2
http://www.hpmuseum.net/document.php?hwfile=4049
3
http://www.hpmuseum.net/document.php?hwfile=3343
4
http://www.hpmuseum.net/document.php?hwfile=4048
5
http://findarticles.com/p/articles/mi_m0HPJ/is_n3_v40/ai_7397316
6
http://www.hpmuseum.net/document.php?hwfile=2652
10
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