HP B160L Manual do Utilizador Página 29

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PA-RISC Processors PA-8200 (PCX-U+) (Vulcan)
Time of introduction
May 1997
Overview
Shortly after the introduction of the PA-8000 the design team noted several aspects of this chip for
improvement in the successor:
Branch prediction
TLB miss rates
Cache sizes
The new chip should offer improved performace, compatibility with existing applications and short
time to market, with the whole design heavily leveraged from the existing PA-8000 foundation. The
availability of new 4Mb SRAMs with faster access times allowed for an increased CPU clock speed
and bigger caches. Smaller changes include an increase to the BHT and TLB as “high benefit, low
risk” improvements.
Details
PA-RISC version 2.0 64-bit
Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2
Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
4-way superscalar
Two address adders
SMP-capable
External memory and I/O controllers
120-entry fully-associative dual-ported TLB
42-entry BTAC (Branch Target Address Cache)
1024-entry BHT (Branch History Table)
Dynamic and static branch prediction modes
Off-chip L1 caches up to 2MB I and 2MB D, realized in synchronous 5ns (200MHz) late-write
4Mb SRAMs, one cycle latency
Caches are direct-mapped and dual-ported
56-entry instruction queue/reorder buffer (IRB)
Each instruction includes five predecode bits
MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG
decoding
Bi-endian support
22
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